Incorrect signal

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pimpim1
Posts: 6
Joined: Wed Aug 21, 2019 7:42 pm

Incorrect signal

Post by pimpim1 » Wed Aug 21, 2019 8:11 pm

Hi,
We use TBS 6590 cards with CI slots. On minisatip web snr level is shown only (13%), but Femon shows ~67% Pleas see attached picture.
Maybe its posible to fix this problem?

Femon shows good snr:
FE: Silicon Labs Si2183 (DVBS)
status SCVYL | signal 61% | snr 68% | ber 0 | unc 0 | FE_HAS_LOCK
status SCVYL | signal 61% | snr 68% | ber 0 | unc 0 | FE_HAS_LOCK
status SCVYL | signal 61% | snr 67% | ber 0 | unc 0 | FE_HAS_LOCK
status SCVYL | signal 61% | snr 68% | ber 0 | unc 0 | FE_HAS_LOCK
status SCVYL | signal 61% | snr 68% | ber 0 | unc 0 | FE_HAS_LOCK
status SCVYL | signal 61% | snr 67% | ber 0 | unc 0 | FE_HAS_LOCK
status SCVYL | signal 61% | snr 68% | ber 0 | unc 0 | FE_HAS_LOCK
^C
root@moiproamd:~# femon -H -a 4 -f 0
FE: Silicon Labs Si2183 (DVBS)
status SCVYL | signal 55% | snr 67% | ber 0 | unc 0 | FE_HAS_LOCK
status SCVYL | signal 54% | snr 67% | ber 0 | unc 0 | FE_HAS_LOCK
status SCVYL | signal 54% | snr 67% | ber 0 | unc 0 | FE_HAS_LOCK
status SCVYL | signal 54% | snr 67% | ber 0 | unc 0 | FE_HAS_LOCK
status SCVYL | signal 54% | snr 67% | ber 0 | unc 0 | FE_HAS_LOCK
status SCVYL | signal 54% | snr 67% | ber 0 | unc 0 | FE_HAS_LOCK
status SCVYL | signal 54% | snr 67% | ber 0 | unc 0 | FE_HAS_LOCK
status SCVYL | signal 54% | snr 67% | ber 0 | unc 0 | FE_HAS_LOCK
^C
root@moiproamd:~# femon -H -a 5 -f 0
FE: Silicon Labs Si2183 (DVBS)
status SCVYL | signal 51% | snr 67% | ber 0 | unc 0 | FE_HAS_LOCK
status SCVYL | signal 51% | snr 67% | ber 0 | unc 0 | FE_HAS_LOCK
status SCVYL | signal 51% | snr 67% | ber 0 | unc 0 | FE_HAS_LOCK
status SCVYL | signal 51% | snr 67% | ber 0 | unc 0 | FE_HAS_LOCK
status SCVYL | signal 51% | snr 67% | ber 0 | unc 0 | FE_HAS_LOCK
status SCVYL | signal 51% | snr 67% | ber 0 | unc 0 | FE_HAS_LOCK
status SCVYL | signal 51% | snr 67% | ber 0 | unc 0 | FE_HAS_LOCK
Attachments
signal.png
signal.png (83.14 KiB) Viewed 1020 times

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